mikecarper
e8d1e537e4
Add receive-only same-image display, SPI, modem/IQ-cache and scoped-priority experiments with checkpointed collectors. Keep rejected clock-phase correction and elevated-priority experiments out of production. Publish sanitized timing data, Full Companion/Bluetooth/USB checks and redraw measurements with their limits. Wire the new behavioral checks into CI.
90 lines
3.4 KiB
C++
90 lines
3.4 KiB
C++
#pragma once
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#include <helpers/radiolib/ESP32BufferedRadioHal.h>
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#include "TDeckSpiClockTiming.h"
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#if defined(CONFIG_IDF_TARGET_ESP32S3) && CONFIG_IDF_TARGET_ESP32S3
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#include <esp_arduino_version.h>
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#if ESP_ARDUINO_VERSION == ESP_ARDUINO_VERSION_VAL(2, 0, 17)
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#include <soc/spi_struct.h>
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#define MESH_TDECK_CLOCK_TIMING_SUPPORTED 1
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#endif
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#endif
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// Experimental HIL-only divider comparison; hardware tests rejected this
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// correction for production because it increased SPI read errors.
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// The T-Deck radio and display both use SPIClass(HSPI), which is GPSPI3 on
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// ESP32-S3. This helper must not be used with an FSPI radio bus. Correction is
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// opt-in and limited to the pinned Arduino core whose divider was inspected.
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class TDeckRadioHal : public ESP32BufferedRadioHal {
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bool _correct_clock_timing = false;
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bool _transaction_open = false;
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bool _restore_clock = false;
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uint32_t _original_clock = 0;
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uint32_t _corrected_clock = 0;
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public:
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explicit TDeckRadioHal(SPIClass& bus, uint32_t hz = MC_SX1262_SPI_HZ)
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: ESP32BufferedRadioHal(bus, hz) {}
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static constexpr bool supportsClockTimingCorrection() {
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#ifdef MESH_TDECK_CLOCK_TIMING_SUPPORTED
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return true;
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#else
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return false;
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#endif
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}
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// Change policy only between transactions. Return false if enabling is
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// unsupported or a transaction is already open; retain the previous policy.
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bool setClockTimingCorrection(bool enabled) {
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if (_transaction_open || (enabled && !supportsClockTimingCorrection())) return false;
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_correct_clock_timing = enabled;
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return true;
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}
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bool isClockTimingCorrectionActive() const { return _correct_clock_timing; }
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// Last transaction's raw values remain available after it ends. They are
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// zero on unsupported cores, where this class retains the ordinary HAL.
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uint32_t getOriginalClockTiming() const { return _original_clock; }
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uint32_t getCorrectedClockTiming() const { return _corrected_clock; }
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void spiBeginTransaction() override {
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ArduinoHal::spiBeginTransaction();
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_transaction_open = true;
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_restore_clock = false;
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#ifdef MESH_TDECK_CLOCK_TIMING_SUPPORTED
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_original_clock = GPSPI3.clock.val;
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_corrected_clock = _correct_clock_timing
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? TDeckSpiClockTiming::corrected(_original_clock) : _original_clock;
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if (_corrected_clock != _original_clock) {
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// The base call already owns both SPI locks. Calling setClockDivider()
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// or spiSetClockDiv() here would try to acquire a held mutex again.
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GPSPI3.clock.val = _corrected_clock;
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GPSPI3.cmd.update = 1;
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while (GPSPI3.cmd.update) {}
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_restore_clock = true;
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}
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#endif
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}
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void spiEndTransaction() override {
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#ifdef MESH_TDECK_CLOCK_TIMING_SUPPORTED
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if (_restore_clock) {
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// Module has released radio CS. Restore the exact original divider while
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// still owning the bus, before the TFT's independent SPIClass can use it.
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GPSPI3.clock.val = _original_clock;
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GPSPI3.cmd.update = 1;
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while (GPSPI3.cmd.update) {}
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}
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#endif
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_restore_clock = false;
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_transaction_open = false;
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ArduinoHal::spiEndTransaction();
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}
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};
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// Correct phase fields do not make every nominal clock valid for the slave:
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// 80 MHz / 5 gives 16 MHz with 25 ns high and 37.5 ns low, whereas / 6 gives
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// 13.333 MHz with 37.5 ns in each phase. Check the SX1262 minimum phase times
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// independently; do not select 16 MHz for production based on frequency alone.
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