mikecarper
e8d1e537e4
Add receive-only same-image display, SPI, modem/IQ-cache and scoped-priority experiments with checkpointed collectors. Keep rejected clock-phase correction and elevated-priority experiments out of production. Publish sanitized timing data, Full Companion/Bluetooth/USB checks and redraw measurements with their limits. Wire the new behavioral checks into CI.
69 lines
2.9 KiB
Python
69 lines
2.9 KiB
Python
"""Check the HIL-only ESP32-S3 radio clock phase experiment under C++11."""
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from pathlib import Path
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import os
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import subprocess
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import tempfile
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import unittest
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ROOT = Path(__file__).resolve().parents[1]
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class TDeckSpiClockTimingTests(unittest.TestCase):
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def test_all_dividers_preserve_frequency_and_correct_only_phase_fields(self):
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fixture = r'''
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#include <cassert>
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#include <cstdint>
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#include <initializer_list>
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#include "TDeckSpiClockTiming.h"
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int main() {
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for (uint32_t pre = 0; pre < 16; ++pre) {
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for (uint32_t n = 0; n < 64; ++n) {
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for (uint32_t h = 0; h < 64; ++h) {
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// Vary L independently too. Include reserved bits so a phase repair
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// cannot silently modify frequency, source selection or other fields.
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const uint32_t l = (h * 19 + 7) & 63;
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const uint32_t original = 0x12400000U | (pre << 18) | (n << 12) | (h << 6) | l;
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const uint32_t corrected = TDeckSpiClockTiming::corrected(original);
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assert((corrected & ~0x0fffU) == (original & ~0x0fffU));
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if (n == 0) assert(corrected == original);
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else {
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assert((corrected & 63) == n);
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assert(((corrected >> 6) & 63) == (n + 1) / 2 - 1);
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assert(TDeckSpiClockTiming::corrected(corrected) == corrected);
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}
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// The undivided source-clock mode must remain completely untouched.
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const uint32_t sourceClock = original | (1U << 31);
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assert(TDeckSpiClockTiming::corrected(sourceClock) == sourceClock);
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}
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}
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}
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// 8 MHz and 10 MHz can use period=2 plus a pre-divider. Their original
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// H=0,L=1 is already correct, so this correction is not a general speed fix.
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for (uint32_t pre : {4U, 3U, 2U}) {
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const uint32_t raw = (pre << 18) | (1U << 12) | 1U;
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assert(TDeckSpiClockTiming::corrected(raw) == raw);
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}
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// At 80 MHz source, /5 is 16 MHz but has 2 high and 3 low source ticks:
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// 25 ns/37.5 ns. /6 with no pre-divider has symmetric 37.5 ns phases.
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const uint32_t divide5 = TDeckSpiClockTiming::corrected((4U << 12) | 2U);
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const uint32_t divide6 = TDeckSpiClockTiming::corrected((5U << 12) | 3U);
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assert(((divide5 >> 6) & 63) + 1 == 2 && (divide5 & 63) == 4);
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assert(((divide6 >> 6) & 63) + 1 == 3 && (divide6 & 63) == 5);
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}
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'''
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with tempfile.TemporaryDirectory() as directory:
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cpp = Path(directory) / "clock.cpp"
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binary = Path(directory) / ("clock.exe" if os.name == "nt" else "clock")
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cpp.write_text(fixture, encoding="ascii")
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built = subprocess.run([os.environ.get("CXX", "g++"), "-std=c++11",
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"-Wall", "-Wextra", "-I", str(ROOT / "tools/hil"), str(cpp), "-o", str(binary)],
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capture_output=True, text=True)
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self.assertEqual(built.returncode, 0, built.stderr)
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ran = subprocess.run([str(binary)], capture_output=True, text=True)
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self.assertEqual(ran.returncode, 0, ran.stderr)
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if __name__ == "__main__":
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unittest.main()
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