mikecarper
a782cc8413
Reuse the confirmed LoRa modem only inside acknowledged warm continuous-RX hops and revoke that capability before modem initialization or after failures. Opt the tested T-Deck into IQ workaround reuse and an exact 8,888,888 Hz SPI setting. Keep the existing BUSY, packet-ownership and recovery checks; other boards retain their modem-cache default.
261 lines
12 KiB
Python
261 lines
12 KiB
Python
"""Execute owned IQ-workaround reuse, wire bytes, revocation and failures."""
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from pathlib import Path
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import os
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import re
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import subprocess
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import tempfile
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import unittest
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from test_radio_receive_contract import method
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import test_sx1262_modem_cache as modem_cache
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ROOT = Path(__file__).resolve().parents[1]
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class ProfileIqCacheTest(unittest.TestCase):
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def test_only_qualified_recipes_opt_in(self):
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opt_ins = []
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for recipe in (ROOT / "variants").glob("*/platformio.ini"):
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if re.search(r"^\s*-D\s+MC_SX1262_FAST_IQ_CACHE=1\s*$",
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recipe.read_text(), re.MULTILINE):
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opt_ins.append(recipe.relative_to(ROOT).as_posix())
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self.assertCountEqual(opt_ins, ["variants/sensecap_indicator-espnow/platformio.ini",
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"variants/lilygo_tdeck/platformio.ini"])
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def compile_run(self, source):
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with tempfile.TemporaryDirectory() as folder:
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cpp = Path(folder) / "test.cpp"
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binary = Path(folder) / ("test.exe" if os.name == "nt" else "test")
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cpp.write_text(source, encoding="ascii")
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sanitizers = [] if os.name == "nt" else [
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"-fsanitize=address,undefined", "-fno-omit-frame-pointer", "-no-pie"]
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built = subprocess.run([os.environ.get("CXX", "g++"), "-std=c++17",
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"-Wall", "-Wextra", *sanitizers, str(cpp), "-o", str(binary)],
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capture_output=True, text=True)
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self.assertEqual(built.returncode, 0, built.stderr)
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ran = subprocess.run([str(binary)], capture_output=True, text=True)
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self.assertEqual(ran.returncode, 0, ran.stderr)
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def test_owned_iq_ack_wire_payload_setters_lifecycle_and_errors(self):
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source = (ROOT / "src/helpers/radiolib/CustomSX1262.h").read_text()
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state = (ROOT / "src/helpers/radiolib/SX1262ProfileSwitchState.h").read_text().replace("#pragma once", "")
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signatures = ("void setProfileSwitchOptimization(", "void beginProfileSwitch(",
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"void endProfileSwitch(", "int16_t reset(bool", "int16_t sleep(bool",
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"int16_t stageMode(", "int16_t setPreambleLength(", "int16_t setCRC(",
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"int16_t implicitHeader(", "int16_t explicitHeader()", "int16_t invertIQ(",
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"int16_t setProfileProtocol(", "int16_t writeRegister(",
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"int16_t setPacketParams(", "int16_t writeProfilePacketParams(",
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"int16_t startReceive()", "int16_t startReceiveDutyCycle(")
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methods = "\n".join(method(source, signature).replace(" override", "") for signature in signatures)
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fixture = r'''
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#include <cassert>
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#include <cstdint>
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#include <cstddef>
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#include <string>
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#include <vector>
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@DEFINES@
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#define MC_SX1262_FAST_PACKET_CACHE 0
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#define RADIOLIB_ERR_NONE 0
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#define RADIOLIB_SX126X_STANDBY_RC 0
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#define RADIOLIB_SX126X_RX_TIMEOUT_INF 0xffffff
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#define RADIOLIB_SX126X_PACKET_TYPE_LORA 1
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#define RADIOLIB_SX126X_CMD_SET_PACKET_PARAMS 0x8c
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#define RADIOLIB_RADIO_MODE_NONE 0
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#define RADIOLIB_IRQ_RX_DEFAULT_FLAGS 1
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#define RADIOLIB_IRQ_RX_DEFAULT_MASK 2
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#define RADIOLIB_IRQ_PREAMBLE_DETECTED 3
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#define RADIOLIB_SX126X_LORA_CRC_ON 1
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#define RADIOLIB_SX126X_LORA_HEADER_EXPLICIT 0
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#define RADIOLIB_SX126X_LORA_IQ_STANDARD 0
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using RadioModeType_t=int;
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using RadioLibIrqFlags_t=uint32_t;
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struct RadioModeConfig_t {};
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@STATE@
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struct Module {
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enum { MODE_RX=1 };
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std::string* trace;char* fail;std::vector<uint8_t> packet;
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int16_t SPIwriteStream(uint16_t command,const uint8_t* data,size_t size) {
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assert(command==0x8c && size==6);packet.assign(data,data+size);
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*trace+='P';return *fail=='P' ? -100:0;
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}
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void setRfSwitchState(int mode) { assert(mode==MODE_RX);*trace+='W'; }
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};
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struct SX1262 {
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std::string trace;char fail=0;int modem=1;bool standbyXOSC=true;
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uint16_t preambleLengthLoRa=32;
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uint8_t crcTypeLoRa=1,headerType=0,invertIQEnabled=0;
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size_t implicitLen=255;
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uint32_t rxTimeout=0;int stagedMode=3;float tcxoVoltage=1.8f;
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Module module{&trace,&fail,{}};Module* mod=&module;
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int16_t call(char c) { trace+=c;return c==fail ? -100:0; }
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Module* getMod() { return mod; }
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int16_t standby(uint8_t) { return call('S'); }
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int16_t sleep(bool) { return call('L'); }
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int16_t reset(bool) { return call('Z'); }
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virtual int16_t stageMode(RadioModeType_t,RadioModeConfig_t*) { return call('G'); }
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int16_t setPacketParams(uint16_t p,uint8_t crc,uint8_t len,uint8_t hdr,uint8_t iq) {
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int16_t rc=call('I');if(!rc) rc=call('i');
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const uint8_t data[]={uint8_t(p>>8),uint8_t(p),hdr,len,crc,iq};
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if(!rc) rc=module.SPIwriteStream(0x8c,data,sizeof(data));return rc;
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}
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virtual int16_t setPreambleLength(size_t p) {
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preambleLengthLoRa=p;return setPacketParams(p,crcTypeLoRa,implicitLen,headerType,invertIQEnabled);
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}
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int16_t setCRC(uint8_t crc,uint16_t,uint16_t,bool) {
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crcTypeLoRa=crc;return setPacketParams(preambleLengthLoRa,crc,implicitLen,headerType,invertIQEnabled);
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}
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int16_t implicitHeader(size_t n) {
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implicitLen=n;headerType=1;
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return setPacketParams(preambleLengthLoRa,crcTypeLoRa,implicitLen,headerType,invertIQEnabled);
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}
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int16_t explicitHeader() {
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implicitLen=255;headerType=0;
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return setPacketParams(preambleLengthLoRa,crcTypeLoRa,implicitLen,headerType,invertIQEnabled);
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}
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virtual int16_t invertIQ(bool enable) {
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invertIQEnabled=enable;
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return setPacketParams(preambleLengthLoRa,crcTypeLoRa,implicitLen,headerType,invertIQEnabled);
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}
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int16_t setSyncWord(uint8_t) { return call('Y'); }
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int16_t writeRegister(uint16_t,const uint8_t*,uint8_t) { return call('J'); }
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int16_t startReceive(uint32_t,uint32_t,uint32_t,size_t) {
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int16_t rc=stageMode(1,nullptr);if(!rc) rc=call('F');
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if(!rc) rc=setPacketParams(preambleLengthLoRa,crcTypeLoRa,implicitLen,headerType,invertIQEnabled);
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if(!rc) rc=call('R');return rc;
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}
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int16_t startReceiveDutyCycle(uint32_t,uint32_t,uint32_t,uint32_t) { return call('D'); }
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uint8_t getPacketType() { call('Q');return modem; }
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int16_t clearIrqStatus() { return call('C'); }
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int16_t setRx(uint32_t timeout) { assert(timeout==0xffffff);return call('R'); }
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};
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struct Radio : SX1262 {
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SX1262ProfileSwitchState _profileSwitch{true};
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bool _coldStandby=true,_tcxoWakePending=false,_rx_ps_rf_rx_disabled=false;
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uint32_t _profileFastResumes=0;
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#ifdef MC_SX1262_HIL
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bool hilSkipUnchangedPacket=false,hilSkipUnchangedIq=true;
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uint32_t hilPacketSkips=0,hilIqWorkaroundSkips=0;
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#endif
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@METHODS@
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};
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void prime(Radio& r) {
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assert(r.startReceive()==0);
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assert(r.trace.find("IiP")!=std::string::npos && r.trace.back()=='Q');
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assert(r._profileSwitch.rxValid && r._profileSwitch.packetValid);
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assert(!r._profileSwitch.matchesPacketIq(r.invertIQEnabled));
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r.trace.clear();
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}
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void arm(Radio& r) {
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r.beginProfileSwitch(true);
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assert(!r._profileSwitch.matchesPacketIq(r.invertIQEnabled));
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r._profileSwitch.standbyResult(0);
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}
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int main() {
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// Only IQ is reused: changing every other packet field still emits its full
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// six-byte command in the exact SX126x wire order, including both pre bytes.
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for(uint8_t iq:{0,1}) {
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Radio r;r.invertIQEnabled=iq;prime(r);arm(r);
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assert(r._profileSwitch.matchesPacketIq(iq));
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r.preambleLengthLoRa=0x1234;r.crcTypeLoRa=2;r.implicitLen=73;r.headerType=1;
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assert(r.startReceive()==0 && r.trace=="CPWR");
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assert(r.module.packet==std::vector<uint8_t>({0x12,0x34,1,73,2,iq}));
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assert(r._profileSwitch.packetValid && r._profileSwitch.packetPreamble==0x1234);
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r.endProfileSwitch(true);
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}
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// A changed IQ or an unacknowledged packet must run the original workaround.
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for(int gate=0;gate<3;++gate) {
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Radio r;prime(r);arm(r);
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if(gate==0) r.invertIQEnabled=1;
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if(gate==1) r._profileSwitch.invalidatePacket();
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#ifdef MC_SX1262_HIL
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if(gate==2) r.hilSkipUnchangedIq=false;
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#else
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if(gate==2) continue;
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#endif
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assert(r.startReceive()==0 && r.trace=="CIiPWR");
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}
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// Owned preamble staging is the intended fast case, unlike an ordinary
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// preamble command. Every ordinary packet/direct-register path revokes IQ.
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{ Radio r;prime(r);arm(r);assert(r.setPreambleLength(64)==0 && r.trace.empty());
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assert(r.startReceive()==0 && r.trace=="CPWR"); }
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for(int setter=0;setter<8;++setter) for(bool failure:{false,true}) {
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Radio r;prime(r);
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if(setter!=4) arm(r);
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r.fail=failure ? (setter==5?'Y':setter==6?'J':'P'):0;
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uint8_t value=4;
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switch(setter) {
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case 0:r.setCRC(2);break;
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case 1:r.implicitHeader(73);break;
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case 2:r.explicitHeader();break;
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case 3:r.invertIQ(false);break;
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case 4:r.setPreambleLength(64);break;
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case 5:r.setProfileProtocol(0x2b);break;
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case 6:r.writeRegister(0x736,&value,1);break;
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case 7:r.setPacketParams(64,1,255,0,0);break;
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}
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assert(!r._profileSwitch.packetValid);
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r.fail=0;r.trace.clear();
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if(failure && setter==5) {
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assert(!r._profileSwitch.rxValid);continue;
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}
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if(setter==4) arm(r);
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assert(!r._profileSwitch.matchesPacketIq(r.invertIQEnabled));
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assert(r.startReceive()==0 && r.trace=="CIiPWR");
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}
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// The acknowledged tuple cannot survive TX/CAD staging, either sleep,
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// reset, RX duty cycling, explicit disable, rollback, or a failed RX command.
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for(int event=0;event<8;++event) for(bool failure:{false,true}) {
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Radio r;prime(r);arm(r);r.fail=failure?'G':0;
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switch(event) {
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case 0:r.stageMode(2,nullptr);break;
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case 1:r.stageMode(3,nullptr);break;
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case 2:r.sleep(true);break;
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case 3:r.sleep(false);break;
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case 4:r.reset();break;
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case 5:r.startReceiveDutyCycle(1000,1000);break;
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case 6:r.setProfileSwitchOptimization(false);break;
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case 7:r.endProfileSwitch(false);break;
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}
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assert(!r._profileSwitch.packetValid && !r._profileSwitch.rxValid);
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assert(!r._profileSwitch.matchesPacketIq(r.invertIQEnabled));
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}
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for(char failure:std::string("CIiPR")) {
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Radio r;prime(r);arm(r);
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if(failure=='I' || failure=='i') r._profileSwitch.invalidatePacket();
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r.fail=failure;assert(r.startReceive()==-100 && r.trace.back()==failure);
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assert(!r._profileSwitch.rxValid && !r._profileSwitch.packetValid);
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r.endProfileSwitch(false);r.fail=0;r.trace.clear();prime(r);
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}
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for(int gate=0;gate<4;++gate) {
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Radio r;prime(r);
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switch(gate) {
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case 0:r.beginProfileSwitch(false);r._profileSwitch.standbyResult(0);break;
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case 1:r.standbyXOSC=false;arm(r);break;
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case 2:r.beginProfileSwitch(true);break;
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case 3:r._profileSwitch.packetResult(-100,32,1,255,0,0);break;
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}
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assert(!r._profileSwitch.matchesPacketIq(0));
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}
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}
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'''.replace("@STATE@", state).replace("@METHODS@", methods)
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for definitions in ("#define MC_SX1262_FAST_IQ_CACHE 1",
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"#define MC_SX1262_FAST_IQ_CACHE 0\n#define MC_SX1262_HIL"):
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with self.subTest(definitions=definitions):
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self.compile_run(fixture.replace("@DEFINES@", definitions))
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def test_unqualified_boards_keep_the_original_live_modem_query_and_iq_path(self):
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source = (ROOT / "src/helpers/radiolib/CustomSX1262.h").read_text()
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self.assertIn("#define MC_SX1262_FAST_IQ_CACHE 0", source)
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self.assertIn("#define MC_SX1262_FAST_MODEM_CACHE 0", source)
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# Execute the shared production-method fixture: default-off builds must
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# query the modem, while opted-in/HIL reuse must retain all ownership,
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# initialization and failure gates. Do not depend on an if's spelling.
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modem_cache.ModemCacheTests.test_confirmed_modem_requires_owned_warm_rx_and_survives_no_failure(self)
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helper = method(source, "int16_t writeProfilePacketParams(")
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self.assertIn("return getMod()->SPIwriteStream(RADIOLIB_SX126X_CMD_SET_PACKET_PARAMS,", helper)
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if __name__ == "__main__":
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unittest.main()
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