mikecarper
bd30388436
Keep TCXO warm during owned dual-profile retunes, batch modulation setup, and enable guarded fast RX with buffered 8 MHz SPI on XIAO S3 WIO and Indicator LoRa. Preserve lifecycle invalidation, packet guards, rollback, and existing scheduling budgets. Add reliable sequence-scoped USB lab transport, native regression coverage, bounded channel and preamble diagnostics, and byte-exact measurement records including failed experiments and qualification limits.
46 lines
1.9 KiB
C
46 lines
1.9 KiB
C
#pragma once
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// HIL only. Observe existing SPI reads/clears without changing their bytes.
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// Optional early IRQ polling is performed by the channel scheduler, not here.
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struct ChannelTraceEvent {
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uint32_t us, a, b;
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uint16_t irq;
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uint8_t channel, kind;
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};
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struct ChannelTrace {
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enum : uint8_t { Arm=1, Irq=2, Clear=3, Hop=4, Hold=5, Packet=6, Timeout=7 };
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static constexpr unsigned Capacity=4096;
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ChannelTraceEvent events[Capacity];
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bool active=false, enabled=false;
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unsigned size=0, overflow=0;
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uint32_t origin=0, sequence=0, pollAt=0, pollCount=0, pollTotalUs=0, pollMaxUs=0;
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uint16_t irq=0;
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uint32_t rfWord=0, txWord=0, txCommandUs=0;
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uint8_t channel=0;
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void add(uint8_t kind,uint32_t a=0,uint32_t b=0) {
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if(!active) return;
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if(size==Capacity) { ++overflow;return; }
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events[size++]={uint32_t(micros()-origin),a,b,irq,channel,kind};
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}
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void arm(uint32_t seq,uint8_t current,uint8_t expected,uint32_t visitAge) {
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size=overflow=0;origin=micros();sequence=seq;channel=current;irq=0;
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pollAt=origin;pollCount=pollTotalUs=pollMaxUs=0;active=enabled;
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add(Arm,expected,visitAge);
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}
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void observe(const uint8_t* out,size_t len,const uint8_t* in) {
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if(!out || !in) return;
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// Track actual command bytes even outside a capture, not just SW labels.
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if(len==5 && out[0]==0x86)
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rfWord=uint32_t(out[1])<<24 | uint32_t(out[2])<<16 | uint32_t(out[3])<<8 | out[4];
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if(len==4 && out[0]==0x83) { txCommandUs=micros();txWord=rfWord; }
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if(!active) return;
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// Pinned SX126x Module: opcode, status dummy, two big-endian IRQ bytes.
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if(len==4 && out[0]==0x12) {
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const uint16_t value=uint16_t(in[2])<<8 | in[3];
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if(value!=irq) { irq=value;add(Irq); }
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} else if(len==3 && out[0]==0x02 && irq) {
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add(Clear,uint16_t(out[1])<<8 | out[2]);
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// Do not predict the clear's success: next actual read establishes it.
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}
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}
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} channelTrace;
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