Keep unqualified SPIM3 workaround and clock settings out of release defaults
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@@ -11,18 +11,11 @@
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#ifndef MC_RAK3401_SPI_HZ
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#define MC_RAK3401_SPI_HZ 8000000
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#endif
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#if MC_RAK3401_SPI_HZ != 2000000 && MC_RAK3401_SPI_HZ != 4000000 \
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&& MC_RAK3401_SPI_HZ != 8000000 && MC_RAK3401_SPI_HZ != 16000000
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#error "RAK3401 radio SPI clock must be 2, 4, 8 or 16 MHz"
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#endif
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#if MC_RAK3401_SPI_HZ == 16000000
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#if !defined(SPI_32MHZ_INTERFACE) || SPI_32MHZ_INTERFACE != 1
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#error "RAK3401 16 MHz radio requires SPI1 on SPIM3 (SPI_32MHZ_INTERFACE=1)"
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#endif
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#if !defined(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) \
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|| NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED != 1
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#error "RAK3401 16 MHz radio requires the global nrfx SPIM3 anomaly 198 workaround"
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#endif
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#if MC_RAK3401_SPI_HZ > 8000000
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#error "RAK3401 SPI above 8 MHz needs an unimplemented SoftDevice-compatible SPIM3 mitigation"
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#elif MC_RAK3401_SPI_HZ != 2000000 && MC_RAK3401_SPI_HZ != 4000000 \
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&& MC_RAK3401_SPI_HZ != 8000000
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#error "RAK3401 radio SPI clock must be 2, 4 or 8 MHz"
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#endif
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namespace {
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@@ -143,9 +136,9 @@ RAK3401Board board;
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// controller instance for startup and watchdog recovery; resetting the radio
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// must not replace or tear down the SPI object used by its Module.
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// Batch each RadioLib command into one SPIM transfer rather than starting a
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// transfer per byte. Keep 8 MHz by default. A 16 MHz HIL comparison must move
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// SPI1 to SPIM3 for the whole framework build and enable its DMA workaround;
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// changing the speed never replaces this bus or its recovery/handoff path.
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// transfer per byte. Keep 8 MHz by default on SPI1/SPIM2. Higher speeds need
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// a separate SPIM3/SoftDevice mitigation before they can be offered safely.
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// Changing the speed never replaces this bus or its recovery/handoff path.
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static Nrf52BufferedRadioHal radioHal(SPI1, MC_RAK3401_SPI_HZ);
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RADIO_CLASS radio = new Module(&radioHal, P_LORA_NSS, P_LORA_DIO_1, P_LORA_RESET, P_LORA_BUSY);
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